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technical note general-purpose operational amplifier/comparator low voltage cmos operational amplifier bu7261g ,bu7261sg, BU7241G,bu7241sg, bu7262f/fvm,bu7262s f/fvm, bu7242f/fvm,bu7242s f/fvm description cmos op-amp bu7261/bu7241 family and bu7262/bu7242 family are input and output full swing op-amp. these ics integrate one op-amp or two independent op-amps and phase compensation capacitor on a single chip. the features of these ic s are low operating supply voltage +1.8v to +5.5v(single supply) and low supply current, extremely low input bias current. features 1) low operating supply voltage ( 1.8[v] 5.5[v]) 8) internal esd protection 2) 1.8 [v] to 5.5[v](single supply) human bod y model (hbm) 4000[v](typ.) 0.9[v] to2.75[v](split supply) 9) wide temperature range 3) input and output full swing 40[ ] to 85[ ] 4) internal phase compensation (bu7261g,bu7262 family, BU7241G,bu7242 family) 5) high slew rate(bu7261 family, bu7262 family) 40[ ] to 105[ ] 6) low supply current(bu7241 family, bu7242 family) (bu7261sg,bu7262s family, bu7241sg,bu7242s family) 7) high large signal voltage gain pin assignments 2007. octber high speed single bu7261 g dual (bu7261sg:105 ) bu7262 f/fvm (bu7262s f/fvm:105 ) low pow er single bu7241 g dual (bu7261sg:105 ) bu7242 f/fvm (bu7242s f/fvm:105 ) 1 2 3 4 8 7 5 out1 in1- in1+ vss vdd out2 in2- in2+ ch1 - + ch2 + - 6 1 2 3 5 4 in+ vss in- vdd out + - sop8 ssop5 msop8 bu7262f bu7262sf bu7242f bu7242sf bu7262fvm bu7262sfvm bu7242fvm bu7242sfvm bu7261g bu7261sg BU7241G bu7241sg
2/16 v! absolute maximum rating d ta=25[ h ] e rating parameter symbol bu7261g bu7262 f/fvm BU7241G bu7242 f/fvm bu7261sg bu7262s f/fvm bu7241sg bu7242s f/fvm uni supply voltage vdd-vss v 7 v differential input voltage(*1) vid vdd w vss v input common-mode voltage range vicm (vss w 0.3) to vdd v 0.3 v operating temperature topr w 40 to v 85 w 40 to v 105 h! storage temperature ts t g w 55 to v 125 h! maximum junction temperature tjmax v 125 h! note: absolute maximum rating item indicate s the condition which must not be exceeded. !! application of voltage in excess of absolute maximum rating or use out absoluted maximum rated temperature environment may c ause deterioration of characteristics. (*1) ! the voltage difference between inverting input and non-inverting input is the differential input voltage. then input terminal voltage is set to more then vee. v! electrical characteristics !u bu7261 series, bu7262series (unless other wise specified vdd=+3[v], vss=0[v], ta=25[ h^*! guaranteed limit bu7261g bu7261sg bu7262 f/fvm bu7262s f/fvm parameter symbol temperature range min. typ. max. min. typ. max. unit condition 25 h - 1 9 - 1 9 input offset voltage (*2)(*4) vio full range - - 10 - - 10 mv vdd=1.8 to 5.5[v], vout=vdd/2 input offset current (*2) iio 25 h! - 1 - - 1 - pa w input bias current (*2) ib 25 h! - 1 - - 1 - pa w 25 h! - 250 550 - 550 1100 supply current (*4) idd full range - - 600 - - 1200 a rl= a all op-amps av=0[db],vin=1.5[v] high level output voltage voh 25 h! vdd-0.1 - - vdd-0.1 - - v rl=10[k ? ? ? input common-mode voltage range vicm 25 h! 0 - 3 0 - 3 v vdd-vss=3[v] common-mode rejection ratio cmrr 25 h! 45 60 - 45 60 - db w power supply rejection ratio psrr 25 h! 60 80 - 60 80 - db w output source current (*3) ioh 25 h! 4 10 - 4 10 - ma vdd-0.4[v] output sink current (*3) iol 25 h! 5 12 - 5 12 - ma vss+0.4[v] slew rate sr 25 h! - 1.1 - - 1.1 - v/s cl=25[pf] gain bandwidth product ft 25 h! - 2 - - 2 - mhz cl=25[pf], av=40[db] phase margin temperature range min. typ. max. min. typ. max. unit condition 25 h! - 1 9 - 1 9 input offset voltage (*5)(*7) vio full range ! - - 10 - - 10 mv vdd=1.8 to 5.5[v], vout=vdd/2 input offset current (*5) iio 25 h! - 1 - - 1 - pa w input bias current (*5) ib 25 h! - 1 - - 1 - pa w 25 h! - 70 150 - 180 360 supply current (*7) idd full range - - 250 - - 600 a rl= a all op-amps av=0[db],vin=1.5[v] high level output voltage voh 25 h! vdd-0.1 - - vdd-0.1 - - v rl=10[k ? ? ? input common-mode voltage range vicm 25 h! 0 - 3 0 - 3 v vdd-vss=3[v] common-mode rejection ratio cmrr 25 h! 45 60 - 45 60 - db w power supply rejection ratio psrr 25 h! 60 80 - 60 80 - db w output source current (*6) ioh 25 h! 4 10 - 4 10 - ma vdd-0.4[v] output sink current (*6) iol 25 h! 5 12 - 5 12 - ma vss+0.4[v] slew rate sr 25 h! - 0.4 - - 0.4 - v/s cl=25[pf] gain bandwidth product ft 25 h! - 0.9 - - 0.9 - mhz cl=25[pf], av=40[db] phase margin
3/16 v example of electrical characteristics !u bu7261 family ! (*) the above date is ability value of sample, it is not guaranteed. bu7261g !w 40[ h ] to v 85[ h ] ! bu7261sg !w 40[ h ] to v 105[ h ] 0 2 4 6 123456 supply voltage [v] output voltage high [v] fig.7 output voltage ? supply voltage (rl=10[k ? output sink current ? ambient temperature (vout=vss+0.4[v]) 0 200 400 600 800 1000 123456 supply voltage [v] supply current [a] -40 h! 25 h! 85 h 105 h! bu7261 family fig.3 supply current ? supply voltage 0 200 400 600 800 1000 -60 -30 0 30 60 90 120 ambient temperature [ b] ] supply current [a] 1.8v 5.5v 3.0v fig.4 supply current ? ambient temperature bu7261 family -40 h! 25 h 85 h 105 h bu7261 family fig.5 output voltage high ? supply voltage (rl=10[k ? output voltage ? ambient temperature (rl=10[k ? output voltage low ? ambient temperature (rl=10[k ? output sink current ? output voltage (vdd=3[v]) fig.1 derating curve 0 200 400 600 800 0 50 100 150 ambient temperature [ b] ] power dissipation [mw] . bu7261g 85 bu7261 family 0 200 400 600 800 0 50 100 150 ambient temperature [ b] ] power dissipation [mw] . 105 bu7261 family fig.2 derating curve bu7261sg 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [ b] ] output source current [ma] 1.8v 5.5v 3.0v fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) bu7261 family 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 output voltage [v] output source current [ma] -40 h 25 h! 85 h! 105 h fig.9 output source current ? output voltage (vdd=3.0[v]) bu7261 family
4/16 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [ b] ] large signall voltage gain [db] u bu7261 family (*) the above date is ability value of sample, it is not guaranteed. bu7261g !w 40[ h ] to v 85[ h ] ! bu7261sg !w 40[ h ] to v 105[ h ] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ b] ] input offset voltage [mv] 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency [hz] gain[db] 0 50 100 150 200 phase [deg] fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) 0 20 40 60 80 100 120 123 456 supply voltage [v] common mode rejection ratio [db] -40 h! 25 h! 85 h! 105 h! bu7261 family 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] 40 h! 25 h! 85 h! 105 h! bu7261 family fig.16 large signal voltage gain ? supply voltage fig.20 power supply rejection ratio ? ambient temperature 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ b] ] power supply rejection ratio [db] bu7261 family 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ b] ] common mode rejection ratio [db] 5.5v 1.8v 3.0v bu7261 family fig.19 common mode rejection ratio ? ambient temperature (vdd=3[v]) 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ b] ] slew rate l-h [v/s] 5.5v 1.8v 3.0v fig.21 slew rate l-h ? ambient temperature bu7261 family 0.0 0.5 1.0 1.5 2.0 2.5 -60 -30 0 30 60 90 120 ambient temperature [ b] ] slew rate h-l [v/s] 5.5v 1.8v 3.0v bu7261 family fig.22 slew rate h-l ? ambient temperature phase gain fig.23 gain - frequency bu7261 family -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage [v] input offset voltage [mv] -40 h! 25 h 85 h! 105 h! bu7261 family fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=1.5[v]) 5.5v 1.8v 3.0v bu7261 family fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=1.5[v]) -15 -10 -5 0 5 10 15 -1 0 1 2 3 4 input voltage [v] input offset voltage [mv] -40 h! 25 h! 85 h! 105 h! fig.15 input offset voltage ? input voltage (vdd=3[v]) bu7261 family fig.17 large signal voltage gain ? ambient temperature bu7261 family 5.5v 1.8v 3.0v
5/16 u bu7262 family (*) the above date is ability value of samp le, it is not guaranteed. bu7262 f/fvm !w 40[ h ] to v 85[ h ] ! bu7262s f/fvm !w 40[ h ] to v 105[ h ] 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 output voltage [v] output source current [ma] 0 400 800 1200 1600 2000 123456 supply voltage [v] supply current [a] 0 20 40 60 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output sink current [ma] 0 5 10 15 20 25 123456 supply voltage [v] output voltage low [mv] 0 300 600 900 1200 1500 -60-30 0 30 60 90120 ambient temperature [ b] ] supply current [a] 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ b] ] power dissipation [mw] . 85 h -40 h 25 h 105 h bu7262 family fig.3 supply current ? supply voltage 3.0v 1.8v 5.5v fig.4 supply current ? ambient temperature bu7262 family -40 h! 25 h 85 h 105 h! fig.7 output voltage low ? supply voltage (rl=10[k ? output voltage high ? supply voltage (rl=10[k ? output voltage high ? ambient temperature (rl=10[k ? output voltage low ? ambient temperature (rl=10[k ? output sink current-output voltage (vdd=3[v]) 0 10 20 30 40 -60 -30 0 30 60 90 120 ambient temperature[ b] ] output sink current [ma] 5.5v 1.8v 3.0v bu7262 family fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) fig.1 derating curve 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ b] ] power dissipation [mw] . bu7262f bu7262fvm 85 bu7262 family fig.2 derating curve bu7262sf bu7262sfvm 105 bu7262 family 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [ b] ] output source current [ma] 5.5v fig.10 output source current ? ambient temperature (vout=vdd-0.4v) bu7262 family -40 h 25 h 85 h 105 h fig.9 output source current ? output voltage (vdd=3.0[v]) bu7262 family 3.0v 1.8v
6/16 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [ b] ] large signal voltage gain [db] u bu7262 family (*) the above date is ability value of samp le, it is not guaranteed. bu7262 f/fvm !w 40[ h ] to v 85[ h ] ! bu7262s f/fvm !w 40[ h ] to v 105[ h ] 0 20 40 60 80 100 120 - 60 - 30 0 30 60 90 120 ambient temperature [ b] ] power supply rejection ratio [db] 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ b] ] common mode rejection ratio [db] -15 -10 -5 0 5 10 15 -1 0 1 2 3 4 input voltage [v] input offset voltage [mv] fig.20 power supply rejection ratio ? ambient temperature bu7262 family 0 1 2 3 4 5 - 60 - 30 0 30 60 90 120 ambient temperature [ b] ] slew rate l-h [v/s] 5.5v 1.8v 3.0v fig.21 slew rate l-h ? ambient temperature bu7262 family 0.0 0.5 1.0 1.5 2.0 2.5 -60 -30 0 30 60 90 120 ambient temperature [ b] ] slew rate h-l [v/s] 5.5v 1.8v 3.0v bu7262 famil y fig.22 slew rate h-l ? ambient temperature 0 20 40 60 80 100 1.e+ 00 1.e+02 1.e+ 04 1.e+06 1.e+ 08 frequency [hz] gain [db] 0 50 100 150 200 phase [deg] phase gain fig.23 gain - frequency bu7262 family -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage[v] input offset voltage [mv] -40 h 25 h 85 h 105 h bu7262 family fig.13 input offset voltage ? supply voltage (vicm=vdd,vout=1.5[v]) 5.5v 1.8v 3.0v fig.17 large signal voltage gain ? ambient temperature bu7262 family bu7262 family -40 h 25 h 85 h 105 h fig.15 input offset voltage ? input voltage (vdd=3[v]) fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) 0 20 40 60 80 100 120 123456 supply voltage [v] common mode rejection ratio [db] -40 h 25 h 85 h 105 h bu7262 family 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] -40 h 25 h! 85 h! 105 h bu7262 family fig.16 large signal voltage gain fig.19 common mode rejection ratio ? ambient temperature (vdd=3[v]) bu726 family 5.5v 1.8v 3.0v fig.14 input offset voltage ? ambient temperature (vicm=vdd,vout=1.5[v]) -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 - 30 0 30 60 90 120 ambient temperature [ b] ] input offset voltage [mv] 1.8v 5.5v 3.0v bu7262 family
7/16 u bu7241 family (*) the above date is ability value of sample, it is not guaranteed. BU7241G !w 40[ h ] to v 85[ h ] ! bu7241sg !w 40[ h ] to v 105[ h ] 0 50 100 150 200 250 - 60 - 30 0 30 60 90 120 supply voltage [v] supply current [a] 0 10 20 30 40 50 60 123456 supply voltage [v] output voltage low [mv] 0 20 40 60 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output sink current [ma] 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 output voltage [v] output source current [ma] 0 50 100 150 200 250 123456 supply voltage [v] supply current [a] 0 200 400 600 800 0 50 100 150 ambient temperature [ b] ] power dissipation [mw] . 0 10 20 30 40 50 60 -60 - 30 0 30 60 90 120 ambient temperature [ b] ] output voltage low [mv] fig.8 output voltage low ? ambient temperature (rl=10[k ? derating curve 0 2 4 6 8 123 456 supply voltage [v] output voltage high [v] fig.5 output voltage high ? supply voltage (rl=10[k ? output voltage high ? ambient temperature (rl=10[k ? output voltage low ? supply voltage (rl=10[k ? output sink current ? output voltage (vdd=3[v]) -40 h 25 h 85 h 105 h 0 10 20 30 40 -60 - 30 0 30 60 90 120 ambient temperature [ b] ] output sink current [ma] bu7241 family fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) 5.5v 1.8v 3.0v fig.3 supply current ? supply voltage bu7241 family -40 h 25 h 85 h 105 h fig.4 supply current ? supply voltage bu7241 family 1.8v 5.5v 3.0v 0 200 400 600 800 050100150 ambient temperature [ b] ] power dissipation [mw] . bu7241sg 105 fig.2 derating curve bu7241 family fig.9 output source current ? output voltage (vdd=3.0[v]) bu7241 family -40 h 25 h 85 h 105 h 0 5 10 15 20 -60-30 0 306090120 ambient temperature [ b] ] output source current [ma] fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) bu7241 family 1.8v 5.5v 3.0v
8/16 u bu7241 family (*) the above date is ability value of sample, it is not guaranteed. BU7241G !w 40[ h ] to v 85[ h ] ! bu7241sg !w 40[ h ] to v 105[ h ] ! fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=1.5[v]) 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency[hz] gain [db] 0 50 100 150 200 phase [deg] 0.0 0.5 1.0 1.5 2.0 -60 -30 0 30 60 90 120 ambient temperature [ b] ] slew rate h-l [v/s] 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ b] ] common mode rejection ratio [db] 0 20 40 60 80 100 120 123 456 supply voltage [v] common mode rejection ratio [db] fig.15 input offset voltage ? input voltage (vdd=3[v]) 60 80 100 120 140 160 - 60 -30 0 30 60 90 120 ambient temperature [ b] ] large signal voltage gain [db] fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=1.5[v]) -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage [v] input offset voltage [mv] 60 80 100 120 140 160 123 456 supply voltage [v] large signal voltage gain [db] -40 h 25 h 85 h 105 h bu7241 family fig.16 large signal voltage gain ? supply voltage bu7241 family fig.17 large signal voltage gain ? ambient tem p erature 5.5v 1.8v 3.0v fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) bu7241 family -40 h 25 h 85 h 105 h fig.19 common mode rejection ratio (vdd=3[v]) bu7241 family 5.5v 1.8v 3.0v 0 30 60 90 120 150 - 60 - 30 0 30 60 90 120 ambient temperature [ b] ] power supply rejection ratio [db] bu7241 family fig.20 power supply rejection ratio ? ambient temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - 60 - 30 0 30 60 90 120 ambient temperature [ b] ] slew rate l-h [v/s] fig.21 slew rate l-h ? ambient temperature bu7241 family 5.5v 1.8v 3.0v bu7241 family fig.22 slew rate h-l ? ambient temperature 5.5v 1.8v 3.0v bu7241 family -40 h 25 h 85 h 105 h -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ b] ] input offset voltage [mv] 5.5v 1.8v 3.0v bu7241 family -15 -10 -5 0 5 10 15 -1 0 1 2 3 4 input voltage [v] input offset voltage [mv] -40 h 25 h 85 h 105 h bu7241 family fig.23 gain - frequency bu7241 family phase gain
9/16 u bu7242 family (*) the above date is ability value of sa mple, it is not guaranteed. bu7242f/fvm !w 40[ h ] to v 85[ h ] ! bu7242sf/fvm !w 40[ h ] to v 105[ h ] 0 200 400 600 800 123456 supply voltage [v] supply current [a] 85 h! -40 h 25 h 105 h bu7242 family fig.3 supply current ? supply voltage 0 200 400 600 800 -60 -30 0 30 60 90 120 ambient temperature [ b] ] supply current [a] 3.0v 1.8v 5.5v fig.4 supply current ? ambient temperature bu7242 family 0 5 10 15 20 25 123456 supply voltage [v] output voltage low [mv] -40 h 25 h 85 h 105 h fig.7 output voltage low ? supply voltage (rl=10[k ? output voltage high ? supply voltage (rl=10[k ? output voltage low ? ambient temperature (rl=10[k ? output sink current ? output voltage (vdd=3[v]) -40 h 25 h 85 h 105 h bu7242 family 0 10 20 30 40 -60 -30 0 30 60 90 120 ambient temperature[ b] ] output sink current [ma] 5.5v 1.8v 3.0v bu7242 family fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) 0 2 4 6 8 -60 -30 0 30 60 90 120 ambient temperature [ b] ] output voltage high [v] 1.8v 5.5v 3.0v fig.6 output voltage high ? ambient temperature (rl=10[k ? derating curve 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ b] ] power dissipation [mw] . bu7242 family bu7242sf bu7242sfvm fig.2 derating curve 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [ b] ] output source current [ma] 1.8v 5.5v 3.0v fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) bu7242 family 0 10 20 30 40 50 00.511.522.53 output voltage [v] output source current [ma] fig.9 output source current ? output voltage (vdd=3.0[v]) -40 h 25 h 85 h 105 h bu7242 family 105
10/16 0 20 40 60 80 100 1.e+00 1.e+02 1.e+04 1.e+06 1.e+08 frequency [hz] gain [db] 0 50 100 150 200 phase [deg] phase gain 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [ b] ] large signal voltage gain [db] u bu7242 family (*) the above date is ability value of sa mple, it is not guaranteed. bu7242f/fvm !w 40[ h ] to v 85[ h ] ! bu7242sf/fvm !w 40[ h ] to v 105[ h ] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -30 0 30 60 90 120 ambient temperature [ b] ] slew rate l-h [v/s] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ b] ] input offset voltage [mv] 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ b] ] power supply rejection ratio [db] 0.0 0.5 1.0 1.5 2.0 -60-30 0 306090120 ambient temperature [ b] ] slew rate h-l [v/s] fig.23 gain - frequency bu7242 family -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage[v] input offset voltage [mv] 5.5v 1.8v 3.0v bu7242 family fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=1.5[v]) 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] 25 h -15 -10 -5 0 5 10 15 -101234 input voltage [v] input offset voltage [mv] 0 20 40 60 80 100 120 12 34 56 supply voltage [v] common mode rejection ratio [db] -40 h 25 h 85 h 105 h fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) bu7242 family 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ b] ] common mode rejection ratio [db] 5.5v 1.8v 3.0v bu7242 family fig.19 common mode rejection ratio ? ambient temperature (vdd=3[v]) fig.20 power supply rejection ratio ? ambient temperature bu7242 family 5.5v 1.8v 3.0v fig.21 slew rate l-h ? ambient temperature bu7242 family 5.5v 1.8v 3.0v bu7242 family fig.22 slew rate h-l ? ambient temperature -40 h 25 h 85 h 105 h bu7242 family fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=1.5[v]) -40 h! 85 h 105 h bu7242 family fig.16 large signal voltage ? supply voltage -40 h 25 h 85 h 105 h fig.15 i nput offset voltage ? input voltage (vdd=3[v]) bu7242 family 5.5v 1.8v 3.0v fig.17 large signal voltage ? ambient temperature bu7242 family
11/16 v! schematic diagram v! test circuit1 null method !! vdd,vss,ek,vicm unit : [v] parameter vf s1 s2 s3 vdd vss ek vicm calculation input offset voltage vf1 on on off 3 0 -1.5 3 1 vf2 -0.5 large signal voltage gain vf3 on on on 3 0 -2.5 1.5 2 vf4 0 common-mode rejection ratio (input common-mode voltage range) vf5 on on off 3 0 -1.5 3 3 vf6 1.8 power supply rejecyion ratio vf7 on on off 5.5 0 -0.9 0 4 w calculation w 1. input offset voltage (vio) 2. large signal voltage gain (av) 3. common-mode rejection ratio (cmrr) 4. power supply rejection ratio (psrr) fig.2 test circuit 1 (one channel only) fig.1 simplified schematic vdd rf =50[k ? ? ? ? ? ? ? ?
12/16 v! test circuit2 switch condition unit: [v] sw no. sw 1 sw 2 sw 3 sw 4 sw 5 sw 6 sw 7 sw 8 sw 9 sw 10 sw 11 sw 12 supply current off off on off on off off off off off off off maximum output voltage rl=10 [k ? ? ? ? ? ? ?
13/16 v description of electrical characteristics described here are the terms of electric characteristics used in this technical note. items and symbols used are also shown. note that item name and symbol and their meaning may differ from those on another manufacture ?s document or general document . 1. absolute maximum ratings absolute maximum rating item indicates the condition which must not be exceeded. application of voltage in excess of absolute maximum rating or use out of absolute maximum rated temper ature environment may cause deter ioration of dharacteristics. 1.1 power supply voltage d vdd/vss e indicates the maximum voltage that can be applied between the posit ive power supply terminal and negative power supply terminal without deterioration or destruction of characteristics of internal circuit. 1.2 ! differential input voltage d vid e indicates the maximum voltage that can be applied between non-invert ing terminal and inverting terminal without deterioration a nd destruction of characteristics of ic. 1.3 ! input common-mode voltage range d vicm e indicates the maximum voltage that can be applied to non-inverting terminal and inverting terminal without deterioration or des truction of characteristics. input common-mode voltage range of the maxi mum ratings not assure normal operation of ic. when normal operation of ic is desired, the input common-mode voltage of characteristics item must be followed. 1.4 ! power dissipation d pd e indicates the power that can be consumed by sp ecified mounted board at the ambient temperature 25 h (normal temperature). ! as for package product, pd is determined by the temperature that can be permitted by ic chip in the package d maximum junction temperature e and thermal resistance of the package 2. electrical characteristics item 2.1 ! input offset voltage d vio e indicates the voltage difference between non-inverting terminal and inverting terminal. it can be translated into the input v oltage difference required for setting the output voltage at 0 [v] 2.2 ! input offset current d iio e indicates the difference of input bias current between non-inverting terminal and inverting terminal. 2.3 ! input bias current d ib e indicates the current that flows into or out of the input te rminal. it is defined by the average of input bias current at non -inverting terminal and input bias current at inverting terminal. 2.4 ! circuit current d icc e indicates the ic current that flows under specified conditions and no-load steady status. 2.5 ! high level output voltage / low level output voltage d voh/vol e indicates the voltage range that can be output by the ic unde r specified load condition. it is typically divided into high-le vel output voltage and low-level output voltage. high-level output voltage indicates the upper limit of output voltage. low-level output voltage i ndicates the lower limit. 2.6 ! large signal voltage gain d av e indicates the amplifying rate (gain) of output voltage against the voltage difference betw een non-inverting terminal and inve rting terminal. it is normally the amplifying rate (gain) with reference to dc voltage. av = (output voltage fluctuation) / (input offset fluctuation) 2.7 input common-mode voltage range d vicm e indicates the input voltage range where ic operates normally. 2.8 common-mode rejection ratio d cmrr e indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. it is normally the fluctua tion of dc. cmrr [d change of input common-mode voltage e / d input offset fluctuation e 2.9 power supply rejection ratio d psrr e indicates the ratio of fluctuation of input offset volt age when supply voltage is changed. it is normally the fluctuation of dc. psrr [d change of power supply voltage e / d input offset fluctuation e 2.10 channel separation d cs e indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage of driven channel. 2.11 slew rate d sr e indicates the time fluctuation ratio of voltage output when step input signal is applied 2.12 unity gain frequency d ft e indicates a frequency where the voltage gain of op-amp is 1. ! 2.13 total harmonic distortion + noise d thd v n e indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage of driven channel 2.14 input referred noise voltage d vn e indicates a noise voltage generated inside the operational amplifier equivalent by ideal voltage source connected in series with input terminal ! ! ! ! !
14/16 v! derating curve ! p ower dissipation (total loss) indicates the power that can be consumed by ic at ta=25 h (normal temperature).ic is heated when it consumed power, and the temperat ure of ic ship becomes hi gher than ambient temperature. the temperature that can be accepted by ic chip depends on circuit configuration, manufacturing process, and consum able power is limited. power dissipation is determined by the temperature allowed in ic chip (maximum junction temperature) and thermal resistance of package (heat dissipation capability). the maximum junction temperature is typically equal to the maximum value in the storage package (heat dissipation capability). the maximum juncti on temperature is typically equal to the maximum value in the storage temperature range. heat generated by consumed power of ic radiates from the mold resin or lead frame of the package. the parameter which indicates this heat dissipation cap ability (hardness of heat release) is called thermal resistance , represented by the symbol M ??
15/16 v! cautions on use 1) absolute maximum ratings absolute maximum ratings are the values which indicate the limits, within which the given voltage range can be safely charged to the terminal. however, it does not guar antee the circuit operation. 2) applied voltage to the input terminal for normal circuit operation of voltage comparator, please input
16/16 v dimensions ! v model number construction packing specification reference ssop5 sop8 msop8 packing specification name ssop5 tr 3000 sop8 e2 2500 msop8 tr 3000 package quantity embossed carrier tape reel direction of feed 1pin 1234 1234 1234 1234 reel direction of feed 1pin 1234 1234 1234 1234 reel 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x direction of feed reel direction of feed 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x g : ssop5 f : sop8 fvm : msop8 u 7262sf - e2 b rohm product name package type e2 embossed tape on reel with pin 1 near far when pulled out tr embossed tape on reel with pin 1 near far when pulled out bu7261 ! bu7261s bu7241 ! bu7241s bu7262 bu7262s bu7242 bu7242s specify the product by the model number when placing an order. make sure of the combinations of items. start with the leftmost space without leaving any empty space between characters.
notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / eupope / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2007 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21, saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix

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